1. Field of the Invention
The present invention relates to a thin film transistor (TFT) and method of fabricating the same and, more particularly, to a TFT and method of fabricating the same in which a capacitor's surface area may be decreased without decreasing its capacity.
2. Discussion of the Background
Generally, a flat panel display device such as an active matrix organic light emitting display (OLED) has a TFT in each pixel, and each pixel may be coupled to a gate line, a data line and a power supply line and further include a capacitor and an organic light emitting diode. A plurality of conductive layers may be used to form a gate line, a gate electrode, a data line, source and drain electrodes, a power supply layer, an anode electrode, and so forth. Such conductive layers may be electrically connected to each other by forming a contact hole in an insulating layer interposed between conductive layers and then burying the conductive layer.
FIG. 1 is a plan view showing a conventional active matrix OLED.
Referring to FIG. 1, the conventional active matrix OLED may include a plurality of gate lines 310, a plurality of data lines 320, a plurality of power supply lines 330, and a plurality of pixels connected to the gate lines 310, the data lines 320, and the power supply lines 330.
Each pixel may include switching and driving TFTs, a capacitor and a light emitting diode. The switching TFT 370 is connected to a gate line 310 and a data line 320, the driving TFT 350 drives the light emitting diode 360 and is connected to the power supply line 330, the capacitor 340 maintains a gate-source voltage of the driving TFT 350, and the light emitting diode 360 emits light to display an image.
The driving TFT 350 has a semiconductor layer 352 including source and drain regions, a gate electrode 354, and source and drain electrodes 356a and 356b connected to the source and drain regions through contact holes 355a and 355b, respectively. The switching TFT 370 may have the same structure.
The capacitor 340 includes a bottom electrode 344 connected to a gate of the driving TFT 350 and, for example, to the drain electrode of the switching TFT 370, and a top electrode 346 connected to the power supply line 330 and, for example, to the source electrode 356a of the driving TFT 350. A pixel electrode 361, which may act as an anode of the light emitting diode having an opening 365, may be connected, for example, to the drain electrode 356b of the driving TFT 350 through a via hole 358.
FIG. 2A and FIG. 2B are cross-sectional views showing a sequence of forming a TFT according to a conventional method.
Referring to FIG. 2A, a buffer layer 110 may be formed on the entire surface of a substrate 100, which is divided into a first region A and a second region B. The buffer layer 110 may be made of silicon oxide having a predetermined thickness, and it may be formed using a plasma-enhanced chemical vapor deposition (PECVD) method. In this case, the buffer layer 110 may prevent impurities from the substrate 100 from penetrating layers above the buffer layer 110.
Next, an amorphous silicon layer (not shown) having a predetermined thickness may be deposited on the buffer layer 110. The amorphous silicon layer may then be crystallized by, for example, excimer laser annealing (ELA), sequential lateral solidification (SLS), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and so forth, and then patterned using photolithography to thereby form polycrystalline silicon layer patterns 120 in the first region A and the second region B within the unit pixel.
A first gate insulating layer 130 may then be formed on the entire surface of the substrate. In this case, the first gate insulating layer 130 may be formed of a silicon oxide (SiO2) layer or a silicon nitride (SiNx) layer, and it may be about 400 Å to 1,000 Å thick.
A photoresist layer pattern (not shown), which corresponds to a channel region of the transistor, may then be formed on the first gate insulating layer 130. Impurity ions may be implanted into the polycrystalline silicon layer pattern 120 using the photoresist layer pattern as an ion implantation mask, thereby forming source and drain regions 122 in the polycrystalline silicon layer pattern 120 in the first region A and a first electrode 124, which may be used as a bottom electrode of a lower capacitor C1, in the polycrystalline silicon layer pattern 120 in the second region B. The photoresist layer pattern may then be removed.
Next, a second gate insulating layer 132 may be formed on the first gate insulating layer 130. The second gate insulating layer 132 may be formed of a SiO2 layer or a SiNx layer, and it may be about 200 Å to 800 Å thick. Alternatively, the second gate insulating layer 132 may be formed before implanting impurity ions into the polycrystalline silicon layer pattern 120 as described above.
A metal layer (not shown) for forming the gate electrode may be formed on the second gate insulating layer 132. The metal layer may be formed of a single layer of molybdenum (Mo) or an alloy such as molybdenum tungsten (MoW), a single layer of aluminum (Al) or an alloy such as aluminum-neodymium (Al—Nd), or a double layer containing these metals. The metal layer may be etched using photolithography to form a gate electrode 134 in the first region A and a second electrode 136, which may be used as a top electrode of the lower capacitor C1, in the second region B. In this case, the second electrode 136 may be used as the top electrode of the lower capacitor C1 and also as a bottom electrode of an upper capacitor C2. Hence, a stacked structure d including the first gate insulating layer 130 and the second gate insulating layer 132 may be used as a dielectric layer of the lower capacitor C1.
An inter-layer insulating layer 140 may then be formed to a predetermined thickness on the entire surface of the substrate. In this case, a SiO2 layer and a SiNx layer may be stacked to form the inter-layer insulating layer 140, which may be about 3,000 Å to 5,000 Å thick.
Referring to FIG. 2B, the inter-layer insulating layer 140, the first gate insulating layer 130, and the second gate insulating layer 132 may then be etched by photolithography to form contact holes exposing the source and drain regions 122, respectively.
An electrode material may then be formed on the entire surface of the substrate including the contact holes and etched using photolithography to form source and drain electrodes 150 and 152, which are connected to the source and drain regions 122, respectively, in the first region A and a third electrode 154, which may be used as a top electrode of the upper capacitor C2 in the second region B. In this case, a single layer of Mo or an alloy such as MoW, a single layer of Al or an alloy such as Al—Nd, or a double layer containing these metals may be employed for the electrode material.
A passivation layer 160, which may be made of an inorganic insulating layer such as a SiNx layer, may then be formed to a predetermined thickness on the entire surface of the substrate.
In the method of fabricating the TFT having the above-mentioned structure, the polycrystalline silicon layer pattern, the gate insulating layers and the gate electrode are used as the lower capacitor C1, and the gate electrode, the inter-layer insulating layer and the drain electrode are used as the upper capacitor C2. The lower capacitor C1 and the upper capacitor C2 are formed within the same area. The lower capacitor C1 has two gate insulating layers as a dielectric layer, and the upper capacitor C2 has the inter-layer insulating layer as a dielectric layer. Hence, a capacitor within a pixel may occupy a relatively large area, and a capacitor having high capacity may be required as devices are highly integrated. However, the capacitor's surface area may need to increase to increase its capacity, which inevitably causes the aperture ratio of the organic light emitting display to decrease.